1. Field of the Invention
The present invention relates to integrated circuit manufacturing, and more particularly to insulated-gate field-effect transistors.
2. Description of Related Art
An insulated-gate field-effect transistor (IGFET), such as a metal-oxide semiconductor field-effect transistor (MOSFET), uses a gate to control an underlying surface channel joining a source and a drain. The channel, source and drain are located in a semiconductor substrate, with the source and drain being doped oppositely to the substrate. The gate is separated from the semiconductor substrate by a thin insulating layer such as a gate oxide. The operation of the IGFET involves application of an input voltage to the gate, which sets up a transverse electric field in order to modulate the longitudinal conductance of the channel.
Polysilicon (also called polycrystalline silicon, poly-Si or poly) thin films have many important uses in IGFET technology. One of the key innovations is the use of heavily doped polysilicon in place of aluminum as the gate. Since polysilicon has the same high melting point as a silicon substrate, typically a blanket polysilicon layer is deposited prior to source and drain formation, and the polysilicon is anisotropically etched to provide a gate. Thereafter, the gate provides an implant mask during the formation of source and drain regions by ion implantation, and the implanted dopants are driven-in and activated using a high-temperature anneal that would otherwise melt the aluminum.
An important parameter in IGFETs is the threshold voltage (V.sub.T), which is the minimum gate voltage required to induce the channel. In general, the positive gate voltage of an N-channel device must be larger than some threshold voltage before a conducting channel is induced, and the negative gate voltage of a P-channel device must be more negative than some threshold voltage to induce the required positive charge (mobile holes) in the channel. There are, however, exceptions to this general rule. For example, depletion-mode devices already have a conductive channel with zero gate voltage, and therefore are normally on. With N-channel depletion-mode devices a negative gate voltage is required to turn the devices off, and with P-channel depletion-mode devices a positive gate voltage is required to turn the devices off.
If the source and body of an IGFET are tied to ground, the threshold voltage can be calculated as follows: EQU V.sub.T =.phi..sub.ms -2.phi..sub.f -Q.sub.tot /C.sub.ox -Q.sub.BO /C.sub.ox -.DELTA.V.sub.T (1)
where .phi..sub.ms is the work-function difference between the gate material and the bulk silicon in the channel, .phi..sub.f is the equilibrium electrostatic potential in a semiconductor, Q.sub.tot is the total positive oxide charge per unit area at the interface between the oxide and the bulk silicon, C.sub.ox is the gate oxide capacitance per unit area, Q.sub.BO is the charge stored per unit area in the depletion region, and .DELTA.V.sub.T is a threshold lowering term associated with short-channel effects. Expressions have been established for these various quantities in terms of doping concentrations, physical constants, device structure dimensions, and temperature. For example, the work-function difference .phi..sub.ms varies as a function of the doping concentration in a polysilicon gate. Therefore, the threshold voltage depends on the doping concentration in the polysilicon gate.
In the event a polysilicon gate is doped solely by the implant steps that provide source/drain doping, in some instances the doping concentration in the polysilicon gate may not be sufficient to provide the desired threshold voltage. Techniques for increasing the doping concentration in a polysilicon gate independently of source/drain doping are known in the art. For instance, the polysilicon layer that is subsequently etched to form the gate can be doped in situ as deposition occurs. In situ doping involves adding dopant gases such as diborane and phosphine to the chemical vapor deposition gases. Although combining doping and deposition in one step may appear simple, the control of film thickness, dopant uniformity, and deposition rate is greatly complicated by the addition of the dopant gases. Moreover, physical properties of the film such as grain size and grain orientation are affected. Alternatively, the polysilicon layer can be doped by solid phase diffusion. An advantage of this approach is its ability to introduce very high concentrations of the dopant in the polysilicon layer, however, a very high temperature is required and the potential exists for increasing the surface roughness. Furthermore, maxmally doped polysilicon films are typically more important for other applications such as high value load resistors used in static memory, and doping studies. As another approach, the polysilicon layer can be doped by ion implantation. The implant energy is usually selected so that the peak concentration of the dopant is located near the center of the polysilicon layer.
The dopant implanted into the gate is subsequently driven-in and activated using high-temperature processing. A high concentration of the dopant needs to be driven to the gate oxide interface in order to avoid increasing the effective thickness of the gate oxide due to polysilicon depletion near the gate oxide interface. In some instances, the temperature needed to drive-in and activate the dopant in the gate is substantially greater than the temperature needed to drive-in and active the source/drain regions. If the same thermal cycle is used, and the dopant in the gate is adequately driven-in, then the source/drain regions may diffuse further into the substrate than is desired. As one solution, U.S. Pat. No. 5,424,229 discloses doping a polysilicon film by annealing in a POCl.sub.3 atmosphere at about 900.degree. C., etching the polysilicon film to form a gate, implanting source/drain regions into the substrate, and then annealing at about 850.degree. C. In this manner, the source/drain regions need not be exposed to the high-temperature processing used during gate formation.
Complementary metal-oxide semiconductor (CMOS) circuits include N-channel (NMOS) devices and P-channel (PMOS) devices. Since boron, a common P-type dopant, tends to diffuse far more rapidly during high-temperature processing than common N-type dopants such as arsenic or phosphorus, it is often desirable to use different anneal temperatures at different stages of the fabrication process.
For instance, a problem encountered in P-channel devices with polysilicon gates containing a high concentration of boron is that when a thin gate oxide is used, poor V.sub.T control may arise due to unwanted boron penetration into the gate oxide, or further, into the underlying channel region. It is reported that boron will penetrate gate oxides that are less than 125 angstroms thick during a 900.degree. C. 30-minute post-implant anneal in nitrogen. It has also been found that the presence of fluorine in the gate oxide worsens the boron penetration problem. Such fluorine can be introduced into the gate oxide if boron difluoride (BF.sub.2) is the implant species. Unfortunately, in some instances, the boron penetration may disruption the threshold voltage.
Accordingly, a need exists for an improved method of making N-channel and P-channel devices that provides adequately doped gates while reducing excessive dopant diffusion.